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FPL
2009
Springer
152views Hardware» more  FPL 2009»
15 years 11 months ago
Clock gating architectures for FPGA power reduction
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
Safeen Huda, Muntasir Mallick, Jason H. Anderson
IDEAS
2000
IEEE
117views Database» more  IDEAS 2000»
15 years 11 months ago
Path Query Reduction and Diffusion for Distributed Semi-Structured Data Retrieval
I n this paper, we address the problem of query processing o n distributed semi-structured data. The distributed semistructured data can be modeled as a rooted and edge-labeled gr...
Jaehyung Lee, Yon Dohn Chung, Myoung-Ho Kim
CISSE
2008
Springer
15 years 8 months ago
Anonymity Leakage Reduction in Network Latency
Each Internet communication leaves trails here or there, that can be followed back to the user. Notably, anonymous communication schemes are purposed to hide users' identity ...
Longy O. Anyanwu, Jared Keengwe, Gladys A. Arome
HAIS
2008
Springer
15 years 7 months ago
Extracting Multi-knowledge from fMRI Data through Swarm-Based Rough Set Reduction
Abstract. Functional Magnetic Resonance Imaging (fMRI) data is collected ceaselessly during brain research, which implicates some important information. It need to be extracted and...
Hongbo Liu, Ajith Abraham, Hong Ye
DAM
2006
97views more  DAM 2006»
15 years 6 months ago
Entity authentication schemes using braid word reduction
Abstract. Artin's braid groups currently provide a promising background for cryptographical applications, since the first cryptosystems using braids were introduced in [2, 3, ...
Hervé Sibert, Patrick Dehornoy, Marc Giraul...