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DATE
2003
IEEE
130views Hardware» more  DATE 2003»
16 years 32 min ago
Noise Macromodel for Radio Frequency Integrated Circuits
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
ICTAI
2003
IEEE
15 years 12 months ago
Engineering Optimization Using a Simple Evolutionary Algorithm
This paper presents a simple ¢¤£¦¥¨§© Evolution Strategy and three simple selection criteria to solve engineering optimization problems. This approach avoids the use of a...
Efrén Mezura-Montes, Carlos A. Coello Coell...
ISCAS
2003
IEEE
119views Hardware» more  ISCAS 2003»
15 years 12 months ago
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning
In this paper, the Simulated Evolution algorithm (SimE) is engineered to solve the optimization problem of multi-objective VLSI netlist bi-partitioning. The multi-objective versio...
Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji
ISQED
2003
IEEE
215views Hardware» more  ISQED 2003»
15 years 12 months ago
Low-Cost and Real-Time Super-Resolution over a Video Encoder IP
This paper addresses a low-cost and real-time solution for the implementation of super-resolution (SR) algorithms over SOC (System-On-Chip) platforms in order to achieve high-qual...
Gustavo Marrero Callicó, Antonio Nú&...
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
15 years 12 months ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...