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ISVLSI
2003
IEEE
97views VLSI» more  ISVLSI 2003»
16 years 4 days ago
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
Andrew B. Kahng, Bao Liu
ICIP
2009
IEEE
16 years 8 months ago
Real Time Stereo Vision Using Exponential Step Cost Aggregation On Gpu
In this paper, we propose a local cost aggregation approach for real time stereo vision on a graphics processing unit (GPU). Recent research shows that local approaches based on c...
VLSID
2002
IEEE
119views VLSI» more  VLSID 2002»
16 years 7 months ago
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
Rituparna Mandal, Dibyendu Goswami, Arup Dash
COCOON
2004
Springer
16 years 8 days ago
Transshipment Through Crossdocks with Inventory and Time Windows
Abstract. The supply chain between manufacturers and retailers always includes transshipments through a network of locations. A major challenge in making demand meet supply has bee...
Andrew Lim, Zhaowei Miao, Brian Rodrigues, Zhou Xu
IJVR
2007
110views more  IJVR 2007»
15 years 6 months ago
Real Time Animation and Illumination in Ancient Roman Sites
—The present article discusses and details the methodological approaches and the reconstruction strategies that have been employed to realize the 3D real-time virtual simulations...
Nadia Magnenat-Thalmann, Alessandro Enrico Foni, G...