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DATE
2002
IEEE
101views Hardware» more  DATE 2002»
15 years 11 months ago
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter
The systematic design of a high-speed, high-accuracy Nyquist A/D converter is proposed. The presented design methodology covers the complete flow and is supported by software tool...
Jan Vandenbussche, Erik Lauwers, K. Uyttenhove, Mi...
DSN
2002
IEEE
15 years 11 months ago
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...
Jiri Gaisler
ISCAS
2002
IEEE
82views Hardware» more  ISCAS 2002»
15 years 11 months ago
Area-efficient digital baseband module for Bluetooth wireless communications
1 This paper describes a small and portable digital baseband module developed for Bluetooth wireless technology. To achieve portability and the small size, much of the Bluetooth ba...
Myoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se...
ISMAR
2002
IEEE
15 years 11 months ago
MR Platform: A Basic Body on Which Mixed Reality Applications Are Built
This paper describes a platform package, called “MR Platform,” which we have been implementing for research and development of augmented reality technology and applications. T...
Shinji Uchiyama, Kazuki Takemoto, Kiyohide Satoh, ...
ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
15 years 11 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
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