10539 search results - page 1896 / 2108 » On L |
166
click to vote
ISCA
2007
IEEE
16 years 25 days ago
2007
IEEE
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
169
click to vote
ISCA
2007
IEEE
16 years 25 days ago
2007
IEEE
There has been considerable recent interest in the support of transactional memory (TM) in both hardware and software. We present an intermediate approach, in which hardware is us...
204
click to vote
ISCA
2007
IEEE
16 years 25 days ago
2007
IEEE
The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applica...
168
click to vote
ISCA
2007
IEEE
16 years 25 days ago
2007
IEEE
The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macromolecules could in principle provide answers to some of the ...
157
click to vote
ISPASS
2007
IEEE
16 years 25 days ago
2007
IEEE
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...