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174
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
175
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...
208
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further use...
195
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
160
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...