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» On Interpolation in Existence Logics
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ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
16 years 3 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 2 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
STACS
2010
Springer
16 years 1 months ago
Branching-time Model Checking of One-counter Processes
One-counter processes (OCPs) are pushdown processes which operate only on a unary stack alphabet. We study the computational complexity of model checking computation tree logic (CT...
Stefan Göller, Markus Lohrey
SAC
2010
ACM
16 years 28 days ago
SE-155 DBSA: a device-based software architecture for data mining
In this paper a new architecture for a variety of data mining tasks is introduced. The Device-Based Software Architecture (DBSA) is a highly portable and generic data mining softw...
Janne Kätevä, Perttu Laurinen, Taneli Ra...
HICSS
2009
IEEE
143views Biometrics» more  HICSS 2009»
16 years 27 days ago
Instance Data Evaluation for Semantic Web-Based Knowledge Management Systems
As semantic web technologies are increasingly used to empower knowledge management systems (KMSs), there is a growing need for mechanisms and automated tools for checking content ...
Jiao Tao, Li Ding, Deborah L. McGuinness