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» On Interpolation in Existence Logics
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DFT
2002
IEEE
103views VLSI» more  DFT 2002»
15 years 11 months ago
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
Thomas Verdel, Yiorgos Makris
ATAL
2001
Springer
15 years 11 months ago
Formalizing a Language for Institutions and Norms
One source of trust for physical trading systems is their physical assets and simply their presence. A similar baseline does not exist for electronic trading systems, but one way i...
Marc Esteva, Julian A. Padget, Carles Sierra
PPDP
2001
Springer
15 years 10 months ago
Constructor-Based Conditional Narrowing
We define a transformation from a left-linear constructor-based conditional rewrite system into an overlapping inductively sequential rewrite system. This transformation is sound...
Sergio Antoy
DAC
1999
ACM
15 years 10 months ago
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
Mauro Chinosi, Roberto Zafalon, Carlo Guardiani
HASE
1998
IEEE
15 years 10 months ago
A Firewalling Scheme for Securing MPOA-Based Enterprise Networks
A well-known security problem with MPOA is that cutthrough connections generally bypasses firewall routers if there are any. None of the previously proposed approaches solved the ...
Jun Xu, Mukesh Singhal