2313 search results - page 92 / 463 » On Heuristic Time Hierarchies |
213
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ISCAPDCS
2004
15 years 7 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
183
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LICS
2005
IEEE
15 years 12 months ago
2005
IEEE
Hierarchical graph definitions allow a modular description of graphs using modules for the specification of repeated substructures. Beside this modularity, hierarchical graph de...
212
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DAC
2012
ACM
13 years 8 months ago
2012
ACM
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
152
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CORR
2007
Springer
15 years 6 months ago
2007
Springer
Efficiently computing fast paths in large-scale dynamic road networks (where dynamic traffic information is known over a part of the network) is a practical problem faced by sever...
196
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APVIS
2011
14 years 6 months ago
2011
We present an efficient method for volume rendering by raycasting on the CPU. We employ coherent packet traversal of an implicit bounding volume hierarchy, heuristically pruned u...