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» On Heuristic Time Hierarchies
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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
16 years 3 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
FOCS
2009
IEEE
16 years 27 days ago
(Meta) Kernelization
Polynomial time preprocessing to reduce instance size is one of the most commonly deployed heuristics to tackle computationally hard problems. In a parameterized problem, every in...
Hans L. Bodlaender, Fedor V. Fomin, Daniel Lokshta...
RTSS
2009
IEEE
16 years 26 days ago
Spatiotemporal Delay Control for Low-Duty-Cycle Sensor Networks
—Data delivery is a major function of sensor network applications. Many applications, such as military surveillance, require the detection of interested events to be reported to ...
Yu Gu, Tian He, Mingen Lin, Jinhui Xu
IPPS
2009
IEEE
16 years 23 days ago
On the complexity of mapping pipelined filtering services on heterogeneous platforms
In this paper, we explore the problem of mapping filtering services on large-scale heterogeneous platforms. Two important optimization criteria should be considered in such a fra...
Anne Benoit, Fanny Dufossé, Yves Robert
MICRO
2009
IEEE
191views Hardware» more  MICRO 2009»
16 years 23 days ago
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches
Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways. First, replacem...
Mainak Chaudhuri