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GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 11 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ISPAN
2005
IEEE
15 years 11 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
COCO
2005
Springer
123views Algorithms» more  COCO 2005»
15 years 11 months ago
If NP Languages are Hard on the Worst-Case Then It is Easy to Find Their Hard Instances
We prove that if NP ⊆ BPP, i.e., if SAT is worst-case hard, then for every probabilistic polynomial-time algorithm trying to decide SAT, there exists some polynomially samplable ...
Dan Gutfreund, Ronen Shaltiel, Amnon Ta-Shma
LCTRTS
2005
Springer
15 years 11 months ago
Cache aware optimization of stream programs
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
Janis Sermulins, William Thies, Rodric M. Rabbah, ...
PPSWR
2005
Springer
15 years 11 months ago
Semantic Web Architecture: Stack or Two Towers?
Abstract. We discuss language architecture for the Semantic Web, and in particular different proposals for extending this architecture with a rules component. We argue that an arch...
Ian Horrocks, Bijan Parsia, Peter F. Patel-Schneid...