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» On Heuristic Time Hierarchies
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ISCC
2006
IEEE
188views Communications» more  ISCC 2006»
16 years 6 days ago
Active Learning Driven Data Acquisition for Sensor Networks
Online monitoring of a physical phenomenon over a geographical area is a popular application of sensor networks. Networks representative of this class of applications are typicall...
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, ...
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
16 years 5 days ago
Scalable Cache Miss Handling for High Memory-Level Parallelism
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
James Tuck, Luis Ceze, Josep Torrellas
ACMMSP
2006
ACM
260views Hardware» more  ACMMSP 2006»
16 years 4 days ago
Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms
A blossoming paradigm for block-recursive matrix algorithms is presented that, at once, attains excellent performance measured by • time, • TLB misses, • L1 misses, • L2 m...
Michael D. Adams, David S. Wise
IMC
2006
ACM
16 years 4 days ago
Quantifying path exploration in the internet
A number of previous measurement studies [10, 12, 17] have shown the existence of path exploration and slow convergence in the global Internet routing system, and a number of prot...
Ricardo V. Oliveira, Beichuan Zhang, Dan Pei, Rafi...
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
16 years 4 days ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl