Sciweavers

2313 search results - page 399 / 463
» On Heuristic Time Hierarchies
Sort
View
IPPS
2010
IEEE
15 years 4 months ago
Towards dynamic reconfigurable load-balancing for hybrid desktop platforms
s the Pus using the OpenCL API as the platform independent programming model. It has the proposal to extend OpenCL with a module that schedule and balance the workload over the CPU...
Alécio Pedro Delazari Binotto, Carlos Eduar...
IJPP
2011
115views more  IJPP 2011»
14 years 9 months ago
Milepost GCC: Machine Learning Enabled Self-tuning Compiler
Tuning compiler optimizations for rapidly evolving hardware makes porting and extending an optimizing compiler for each new platform extremely challenging. Iterative optimization i...
Grigori Fursin, Yuriy Kashnikov, Abdul Wahid Memon...
DAC
2002
ACM
16 years 7 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
16 years 6 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
VLDB
2004
ACM
152views Database» more  VLDB 2004»
16 years 6 months ago
Balancing energy efficiency and quality of aggregate data in sensor networks
In-network aggregation has been proposed as one method for reducing energy consumption in sensor networks. In this paper, we explore two ideas related to further reducing energy co...
Mohamed A. Sharaf, Jonathan Beaver, Alexandros Lab...