2313 search results - page 344 / 463 » On Heuristic Time Hierarchies |
135
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PERCOM
2006
ACM
16 years 6 months ago
2006
ACM
The number of channels specified for IEEE 802.15.4 Low-Rate Wireless Personal Area Networks (LR-WPANs) is too few to operate many applications of WPANs in the same area. To overco...
147
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ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
16 years 3 months ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
138
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
161
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
In macromodeling-based power estimation, circuit macromodels are created from simulations of synthetic input vector sequences. Fast generation of these sequences with all possible...
207
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ISQED
2010
IEEE
16 years 1 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...