2313 search results - page 199 / 463 » On Heuristic Time Hierarchies |
160
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Abstract--To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous res...
189
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
154
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ICCAD
2008
IEEE
16 years 3 months ago
2008
IEEE
Abstract—On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of syst...
145
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for ci...
168
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SAT
2009
Springer
16 years 1 months ago
2009
Springer
We propose a new incomplete algorithm for the Maximum Satisfiability (MaxSAT) problem on unweighted Boolean formulas, focused specifically on instances for which proving unsatis...