Sciweavers

2313 search results - page 184 / 463
» On Heuristic Time Hierarchies
Sort
View
VLSI
2010
Springer
15 years 4 months ago
Fine-grained post placement voltage assignment considering level shifter overhead
—Multi-Vdd techniques enable application of lower supply voltage levels on cells with timing slacks. New voltage assignment, placement and voltage island partitioning methods are...
Zohreh Karimi, Majid Sarrafzadeh
GLOBECOM
2010
IEEE
15 years 4 months ago
Prolonging Network Lifetime via a Controlled Mobile Sink in Wireless Sensor Networks
In this paper we explore the mobility of a mobile sink in a wireless sensor network (WSN) to prolong the network lifetime. Since the mechanical movement of mobile sink is driven by...
Weifa Liang, Jun Luo, Xu Xu
IPPS
1999
IEEE
15 years 10 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
SIGMETRICS
1992
ACM
128views Hardware» more  SIGMETRICS 1992»
15 years 10 months ago
MemSpy: Analyzing Memory System Bottlenecks in Programs
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
Margaret Martonosi, Anoop Gupta, Thomas E. Anderso...
TVCG
2002
132views more  TVCG 2002»
15 years 6 months ago
Hierarchical Pixel Bar Charts
Simple presentation graphics are intuitive and easy-to-use, but only show highly aggregated data. Bar charts, for example, only show a rather small number of data values and x-y-pl...
Daniel A. Keim, Ming C. Hao, Umeshwar Dayal