We present a compiler optimization approach that uses the simulated evolution (SE) paradigm to enhance the finish time of heuristically scheduled computations with communication t...
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
We address in this paper the problem of scheduling for multiprocessor real-time systems with hard and soft tasks. Utility functions are associated to soft tasks to capture their r...
Time triggered methods provide deterministic behaviour suitable for critical real-time systems. They perform less favourably, however, if the arrival times of some activities are ...
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...