Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...
In recent years much attention has been given to providing the proportional delay differentiation through the packet scheduling. The issue of the performance of the scheduling alg...
—In this paper, we present an extended Mobile Backbone Network (MBN) topology synthesis algorithm (ETSA) for constructing and maintaining a dynamic backbone structure in mobile w...
The emerging service grids bring together various distributed services to a ‘market’ for clients to request and enable the integration of services across distributed, heteroge...
— In this paper we address the problem of finding gene regulatory networks from experimental DNA microarray data. We focus on the evaluation of the performance of memetic algori...
Christian Spieth, Felix Streichert, Jochen Supper,...