Sciweavers

7195 search results - page 578 / 1439
» On Computing Power
Sort
View
ICS
2003
Tsinghua U.
16 years 9 days ago
Enhancing memory level parallelism via recovery-free value prediction
—The ever-increasing computational power of contemporary microprocessors reduces the execution time spent on arithmetic computations (i.e., the computations not involving slow me...
Huiyang Zhou, Thomas M. Conte
DAC
2009
ACM
16 years 8 months ago
Process variation characterization of chip-level multiprocessors
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, ...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
16 years 7 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
16 years 7 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
PERCOM
2005
ACM
16 years 6 months ago
Trading Latency for Energy in Wireless Ad Hoc Networks Using Message Ferrying
Power management is a critical issue in wireless ad hoc networks where the energy supply is limited. In this paper, we investigate a routing paradigm, Message Ferrying (MF), to sa...
Hyewon Jun, Wenrui Zhao, Mostafa H. Ammar, Ellen W...