This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mech...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
In many branches of industry, the component-based approach to systems design is predominant, e. g., as in embedded control systems which are often modelled using MATLAB/Simulink. ...
— In this paper, we evaluate a solution based on the preemption mechanism so as to improve performances of distributed Multi-Protocol Label Switching-Traffic Engineering (MPLS-T...