Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural speci...
Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, ...
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In t...
Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. R...
The complexity and physical distribution of modern active-safety automotive applications requires the use of distributed architectures. These architectures consist of multiple ele...
Abhijit Davare, Qi Zhu, Marco Di Natale, Claudio P...
Modern combinational equivalence checking (CEC) engines are complicated programs which are difficult to verify. In this paper we show how a modern CEC engine can be modified to pr...
Satrajit Chatterjee, Alan Mishchenko, Robert K. Br...
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...