This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design di...
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Abstract: This paper addresses the problem of equivalence veriļ¬cation of RTL descriptions that implement arithmetic computations (add, mult, shift) over bitvectors that have diļ¬...
In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reductio...
Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian...