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ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
16 years 3 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
ISSTA
2000
ACM
15 years 11 months ago
Finding bugs with a constraint solver
A method for finding bugs in code is presented. For given small numbers j and k, the code of a procedure is translated into a relational formula whose models represent all executi...
Daniel Jackson, Mandana Vaziri
HASE
2007
IEEE
15 years 10 months ago
Validation Support for Distributed Real-Time Embedded Systems in VDM++
We present a tool-supported approach to the validation of system-level timing properties in formal models of distributed real-time embedded systems. Our aim is to provide system a...
John S. Fitzgerald, Simon Tjell, Peter Gorm Larsen...
CAV
2008
Springer
96views Hardware» more  CAV 2008»
15 years 8 months ago
Implied Set Closure and Its Application to Memory Consistency Verification
Hangal et. al. [3] have developed a procedure to check if an instance of the execution of a shared memory multiprocessor program, is consistent with the Total Store Order (TSO) mem...
Surender Baswana, Shashank K. Mehta, Vishal Powar
SPLC
2010
15 years 8 months ago
Consistent Product Line Configuration across File Type and Product Line Boundaries
Creating a valid software configuration of a product line can require laborious customizations involving multiple configuration file types, such as feature models, domain-specific ...
Christoph Elsner, Peter Ulbrich, Daniel Lohmann, W...