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ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
15 years 10 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
158
Voted
DAC
1993
ACM
15 years 10 months ago
Rotation Scheduling: A Loop Pipelining Algorithm
— We consider the resource-constrained scheduling of loops with interiteration dependencies. A loop is modeled as a data flow graph (DFG), where edges are labeled with the numbe...
Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Me...
SC
1990
ACM
15 years 10 months ago
Loop distribution with arbitrary control flow
Loop distribution is an integral part of transforming a sequential program into a parallel one. It is used extensively in parallelization,vectorization, and memory management. For...
Ken Kennedy, Kathryn S. McKinley
DEXA
2006
Springer
138views Database» more  DEXA 2006»
15 years 10 months ago
A Vector Space Model for Semantic Similarity Calculation and OWL Ontology Alignment
Ontology alignment (or matching) is the operation that takes two ontologies and produces a set of semantic correspondences (usually semantic similarities) between some elements of ...
Rubén Tous, Jaime Delgado
ISLPED
1995
ACM
100views Hardware» more  ISLPED 1995»
15 years 10 months ago
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
Aurobindo Dasgupta, Ramesh Karri