Sciweavers

17409 search results - page 3211 / 3482
» Oblio: Design and Performance
Sort
View
IPPS
2000
IEEE
15 years 11 months ago
Study of a Multilevel Approach to Partitioning for Parallel Logic Simulation
Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitionin...
Swaminathan Subramanian, Dhananjai Madhava Rao, Ph...
ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
15 years 11 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ISORC
2000
IEEE
15 years 11 months ago
Scheduling Solutions for Supporting Dependable Real-Time Applications
This paper deals with tolerance to timing faults in time-constrained systems. TAFT (Time Aware Fault-Tolerant) is a recently devised approach which applies tolerance to timing vio...
F. Sandrini, Felicita Di Giandomenico, Andrea Bond...
MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
15 years 11 months ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
MICRO
2000
IEEE
80views Hardware» more  MICRO 2000»
15 years 11 months ago
Silent stores for free
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
Kevin M. Lepak, Mikko H. Lipasti
« Prev « First page 3211 / 3482 Last » Next »