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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
EMO
2006
Springer
117views Optimization» more  EMO 2006»
15 years 8 months ago
Multiplex PCR Assay Design by Hybrid Multiobjective Evolutionary Algorithm
Abstract. Multiplex Polymerase Chain Reaction (PCR) assay is to amplify multiple target DNAs simultaneously using different primer pairs for each target DNA. Recently, it is widely...
In-Hee Lee, Soo-Yong Shin, Byoung-Tak Zhang
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
15 years 8 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu
BIOCOMP
2006
15 years 8 months ago
A Multi-strategy Approach to Protein Structural Alphabet Design
- The search for structural similarity among proteins can provide valuable insights into their functional mechanisms and their functional relationships. Though the protein 1D seque...
Shih-Yen Ku, Yuh-Jyh Hu
IADIS
2004
15 years 8 months ago
Preliminary Steps in Designing and Implementing a Privilege Verifier for PMI
We have designed and deployed a system that uses X.509 public-key certificates (PKC) and attribute certificates (AC) for access control. This includes an authorization service for...
Diana Berbecaru, Antonio Lioy