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DATE
2006
IEEE
135views Hardware» more  DATE 2006»
16 years 25 days ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
OOPSLA
2004
Springer
16 years 3 days ago
A framework for detecting, assessing and visualizing performance antipatterns in component based systems
Component-based enterprise systems often suffer from performance issues as a result of poor system design. In this paper, we propose a framework to automatically detect, assess an...
Trevor Parsons
DATE
2003
IEEE
135views Hardware» more  DATE 2003»
16 years 2 days ago
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture
This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristic...
Nicola Drago, Franco Fummi, Marco Monguzzi, Giovan...
SBCCI
2003
ACM
115views VLSI» more  SBCCI 2003»
16 years 18 hour ago
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
ICCD
1994
IEEE
69views Hardware» more  ICCD 1994»
15 years 11 months ago
Optimal Design of Self-Damped Lossy Transmission Lines for Multichip Modules
This paper presents a simple and robust method of designing the lossy-transmission-line interconnects in a network for multichip modules. This method uses wire-sizing entirely to ...
Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai