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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 10 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
INFOCOM
2012
IEEE
13 years 9 months ago
Truthful spectrum auction design for secondary networks
Abstract—Opportunistic wireless channel access by nonlicensed users has emerged as a promising solution for addressing the bandwidth scarcity challenge. Auctions represent a natu...
Yuefei Zhu, Baochun Li, Zongpeng Li
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
15 years 11 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
15 years 11 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie