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DAC
2008
ACM
16 years 7 months ago
An 8x8 run-time reconfigurable FPGA embedded in a SoC
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
Sumanta Chaudhuri, Sylvain Guilley, Florent Flamen...
DAC
1998
ACM
16 years 7 months ago
Robust IP Watermarking Methodologies for Physical Design
Increasingly popular reuse-based design paradigms create a pressing need for authorship enforcement techniques that protect the intellectual property rights of designers. We devel...
Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, ...
DAC
1998
ACM
16 years 7 months ago
Approximation and Decomposition of Binary Decision Diagrams
Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in reachability analysis and mode...
Kavita Ravi, Kenneth L. McMillan, Thomas R. Shiple...
DAC
2000
ACM
16 years 7 months ago
Symbolic timing simulation using cluster scheduling
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
Clayton B. McDonald, Randal E. Bryant
DAC
2001
ACM
16 years 7 months ago
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design
Communication-based design represents a formal approach to systemon-a-chip design that considers communication between components as important as the computations they perform. Ou...
Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Ke...