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ICPP
1996
IEEE
15 years 10 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
IPPS
1996
IEEE
15 years 10 months ago
Experience with Parallel Computing on the AN2 Network
Technology trends make it attractive to use workstations connected by a local area network as a multicomputing platform for parallel applications. Achieving acceptable application...
Daniel J. Scales, Michael Burrows, Chandramohan A....
CONCUR
1993
Springer
15 years 10 months ago
Loop Parallelization in the Polytope Model
During the course of the last decade, a mathematical model for the parallelization of FOR-loops has become increasingly popular. In this model, a (perfect) nest of r FOR-loops is r...
Christian Lengauer
ICS
1993
Tsinghua U.
15 years 10 months ago
Dynamic Control of Performance Monitoring on Large Scale Parallel Systems
Performance monitoring of large scale parallel computers creates a dilemma: we need to collect detailed information to find performance bottlenecks, yet collecting all this data ...
Jeffrey K. Hollingsworth, Barton P. Miller
SPAA
1990
ACM
15 years 10 months ago
Analysis of Multithreaded Architectures for Parallel Computing
Multithreading has been proposed as an architectural strategy for tolerating latency in multiprocessors and, through limited empirical studies, shown to offer promise. This paper ...
Rafael H. Saavedra-Barrera, David E. Culler, Thors...