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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
16 years 3 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
ICCAD
2001
IEEE
144views Hardware» more  ICCAD 2001»
16 years 3 months ago
Faster SAT and Smaller BDDs via Common Function Structure
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
SOSP
2001
ACM
16 years 3 months ago
Resilient Overlay Networks
A Resilient Overlay Network (RON) is an architecture that allows distributed Internet applications to detect and recover from path outages and periods of degraded performance with...
David G. Andersen, Hari Balakrishnan, M. Frans Kaa...
SOSP
2007
ACM
16 years 3 months ago
VirtualPower: coordinated power management in virtualized enterprise systems
Power management has become increasingly necessary in large-scale datacenters to address costs and limitations in cooling or power delivery. This paper explores how to integrate p...
Ripal Nathuji, Karsten Schwan
IUI
2009
ACM
16 years 3 months ago
Detecting and correcting user activity switches: algorithms and interfaces
The TaskTracer system allows knowledge workers to define a set of activities that characterize their desktop work. It then associates with each user-defined activity the set of ...
Jianqiang Shen, Jed Irvine, Xinlong Bao, Michael G...
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