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ISCA
2005
IEEE
147views Hardware» more  ISCA 2005»
16 years 12 days ago
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
ISCC
2005
IEEE
16 years 12 days ago
A Label Space Reduction Algorithm for P2MP LSPs Using Asymmetric Tunnels
- Traffic Engineering objective is to optimize network resource utilization. Although several works have been published about minimizing network resource utilization, few works hav...
Fernando Solano, Ramón Fabregat, Yezid Dono...
ISQED
2005
IEEE
120views Hardware» more  ISQED 2005»
16 years 12 days ago
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
This paper presents a novel compact passive modeling technique for high-performance RF passives and interconnects modeled as high-order RLCM circuits. The new method is based on a...
Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
16 years 12 days ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
LCN
2005
IEEE
16 years 12 days ago
Achieving Scalable Capacity in Wireless Networks with Adaptive Power Control
— The seminar work of Gupta and Kumar [1] showed that multi-hop wireless networks with capacity scalable with the number of nodes, n, are achievable in theory. The transport capa...
Ivan Wang Hei Ho, Soung Chang Liew
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