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ICCAD
2007
IEEE
92views Hardware» more  ICCAD 2007»
16 years 3 months ago
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we sug...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
ICCAD
2007
IEEE
125views Hardware» more  ICCAD 2007»
16 years 3 months ago
A methodology for timing model characterization for statistical static timing analysis
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Zhuo Feng, Peng Li
ICCAD
2005
IEEE
107views Hardware» more  ICCAD 2005»
16 years 3 months ago
Projection-based performance modeling for inter/intra-die variations
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations....
Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J...
ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
16 years 3 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
CVPR
2010
IEEE
16 years 3 months ago
Surface Extraction from Binary Volumes with Higher-Order Smoothness
A number of 3D shape reconstruction algorithms, in particular 3D image segmentation methods, produce their results in the form of binary volumes, where a binary value indicates whe...
Victor Lempitsky
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