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» Novel architecture for loop acceleration: a case study
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FPGA
2000
ACM
125views FPGA» more  FPGA 2000»
15 years 9 months ago
Technology mapping for k/m-macrocell based FPGAs
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
Jason Cong, Hui Huang, Xin Yuan
CSMR
2009
IEEE
15 years 10 months ago
Software Clustering Using Dynamic Analysis and Static Dependencies
Decomposing a software system into smaller, more manageable clusters is a common approach to support the comprehension of large systems. In recent years, researchers have focused ...
Chiragkumar Patel, Abdelwahab Hamou-Lhadj, Juergen...
DATE
2005
IEEE
140views Hardware» more  DATE 2005»
15 years 11 months ago
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing
We present a novel, quality-driven, architectural-level approach that trades-off the output quality to enable power-aware processing of multimedia streams. The error tolerance of ...
Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Mar...
ADBIS
2004
Springer
153views Database» more  ADBIS 2004»
15 years 11 months ago
Cooperative Transaction Processing between Clients and Servers
Business rules are often implemented as stored procedures in a database server. These procedures are triggered by various clients, but the execution load is fully centralized on th...
Steffen Jurk, Ulf Leser, José-Luis Marzo
DATE
2003
IEEE
87views Hardware» more  DATE 2003»
15 years 11 months ago
A First Step Towards Hw/Sw Partitioning of UML Specifications
This paper proposes a novel methodology tailored to design embedded systems, taking into account the emerging market needs, such as hw/sw partitioning, object-oriented specificati...
William Fornaciari, P. Micheli, Fabio Salice, L. Z...