325 search results - page 38 / 65 » Non-uniform Instruction Scheduling |
154
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DATE
2008
IEEE
16 years 15 days ago
2008
IEEE
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...
187
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HPCA
1996
IEEE
15 years 10 months ago
1996
IEEE
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
181
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RTAS
2007
IEEE
16 years 10 days ago
2007
IEEE
This paper discusses an approach for supporting soft realtime periodic tasks in Linux on performance asymmetric multicore platforms (AMPs). Such architectures consist of a large n...
193
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HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
156
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ISLPED
2006
ACM
16 years 11 hour ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...