325 search results - page 30 / 65 » Non-uniform Instruction Scheduling |
154
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TVLSI
2002
15 years 5 months ago
2002
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
186
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ISCAPDCS
2001
15 years 7 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
163
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LCTRTS
2007
Springer
16 years 6 days ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
178
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ISSS
1999
IEEE
15 years 10 months ago
1999
IEEE
Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity o...
157
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EUROPAR
1998
Springer
15 years 10 months ago
1998
Springer
Instruction Balanced Time Slicing IBTS allows multiple parallel jobs to be scheduled in a manner akin to the well-known gang scheduling scheme in parallel computers. IBTS however a...