339 search results - page 64 / 68 » Noise-tolerant dynamic circuit design |
158
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DAC
2001
ACM
16 years 7 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
177
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
180
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FPGA
2006
ACM
15 years 9 months ago
2006
ACM
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
189
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TVLSI
2010
15 years 22 days ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
157
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ISCAS
2002
IEEE
15 years 11 months ago
2002
IEEE
We have implemented an aspect of learning and memory in the nervous system using analog electronics. Using a simple synaptic circuit we realize networks with Hebbian type adaptati...