339 search results - page 38 / 68 » Noise-tolerant dynamic circuit design |
160
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DATE
2009
IEEE
16 years 26 days ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
168
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
117
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ISLPED
1996
ACM
15 years 10 months ago
1996
ACM
A 12-b 125 MSPS, digital to analog converter fabricated on a 0.6 micron single poly double metal CMOS process is presented. The design operates on supply voltages from 2.7 to 5.5 ...
173
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HPCA
2005
IEEE
15 years 11 months ago
2005
IEEE
As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increas...
162
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ISPD
2009
ACM
16 years 27 days ago
2009
ACM
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...