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DAC
1999
ACM
15 years 11 months ago
Interconnect Analysis: From 3-D Structures to Circuit Models
In this survey paper we describethe combination of: discretized integral formulations, sparsication techniques, and krylov-subspace based model-order reduction that has led to rob...
Mattan Kamon, Nuno Alexandre Marques, Yehia Massou...
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
15 years 11 months ago
Cycle-based Simulation with Decision Diagrams
This paper addresses the problem of efficient functional simulation of synchronous digital systems. A technique based on the use of Decision Diagrams (DD) for representing the fun...
Raimund Ubar, Jaan Raik, Adam Morawiec
IPPS
1999
IEEE
15 years 11 months ago
Parallel Program Archetypes
A parallel program archetype is an abstraction that captures the common features of a class of problems with similar computational structure and combines them with a parallelizati...
Berna L. Massingill, K. Mani Chandy
VTS
1999
IEEE
71views Hardware» more  VTS 1999»
15 years 11 months ago
Test Generation for Ground Bounce in Internal Logic Circuitry
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
GLVLSI
1998
IEEE
129views VLSI» more  GLVLSI 1998»
15 years 11 months ago
Stochastic Evolution Algorithm For Technology Mapping
A new technology mapper SELF-Map for LookUp Table LUT based Field Programmable Gate Arrays FPGAs is described. SELF-Map is based on the Stochastic Evolution SE algorithm. The stat...
Ahmad S. Al-Mulhem, Alaaeldin Amin, Habib Youssef