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IPPS
1997
IEEE
15 years 11 months ago
Time-Stamping Algorithms for Parallelization of Loops at Run-Time
In this paper, we present two new run-time algorithms for the parallelization of loops that have indirect access patterns. The algorithms can handle any type of loop-carried depen...
Cheng-Zhong Xu, Vipin Chaudhary
ITC
1997
IEEE
129views Hardware» more  ITC 1997»
15 years 11 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
15 years 11 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
DAC
1997
ACM
15 years 11 months ago
Quadratic Placement Revisited
The “quadratic placement” methodology is rooted in [6] [14] [16] and is reputedly used in many commercial and in-house tools for placement of standard-cell and gate-array desi...
Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huan...
DAC
1997
ACM
15 years 11 months ago
Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks
CAD tools and research in the area of reduced-order modeling of largelinearinterconnect networkshaveevolved from merely finding a Pad´e approximation for the given network trans...
Ibrahim M. Elfadel, David D. Ling
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