In this paper, we present two new run-time algorithms for the parallelization of loops that have indirect access patterns. The algorithms can handle any type of loop-carried depen...
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
The “quadratic placement” methodology is rooted in [6] [14] [16] and is reputedly used in many commercial and in-house tools for placement of standard-cell and gate-array desi...
Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huan...
CAD tools and research in the area of reduced-order modeling of largelinearinterconnect networkshaveevolved from merely finding a Pad´e approximation for the given network trans...