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EWC
2000
97views more  EWC 2000»
15 years 6 months ago
Improving the Rationale Capture Capability of QFD
The goals of Design Rationale Capture (DRC) are improving design quality and reducing design time. These general goals have led to the design of many DRC techniques originating fro...
Yoram Reich
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
16 years 7 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng
CLUSTER
2008
IEEE
16 years 1 months ago
Multistage switches are not crossbars: Effects of static routing in high-performance networks
Abstract—Multistage interconnection networks based on central switches are ubiquitous in high-performance computing. Applications and communication libraries typically make use o...
Torsten Hoefler, Timo Schneider, Andrew Lumsdaine
WECWIS
1999
IEEE
164views ECommerce» more  WECWIS 1999»
15 years 11 months ago
Effect of Bargaining in Electronic Commerce
Internet business has grown at an unprecedented rate in the past several years. Recent research has found that the functions provided by a store have a significant impact on custo...
Ting-Peng Liang, Her-Sen Doong
ICCAD
1994
IEEE
105views Hardware» more  ICCAD 1994»
15 years 10 months ago
Register assignment through resource classification for ASIP microcode generation
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
Clifford Liem, Trevor C. May, Pierre G. Paulin