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259
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ISPD
2012
ACM
14 years 2 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
198
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GD
2003
Springer
15 years 12 months ago
2003
Springer
We address the new problem of puzzle layout as a new application of awing. We present two abstract models of puzzles, permutation puzzles and cyclic puzzles, which can be modeled a...
175
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ISCC
2002
IEEE
15 years 11 months ago
2002
IEEE
–– The last few years have seen the evolution of telecommunications from the classic architectures, mainly based on static and wired structures, to the new mobile solutions bas...
157
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CORR
2010
Springer
15 years 6 months ago
2010
Springer
One of the differences among the various approaches to suspension-based tabled evaluation is the scheduling strategy. The two most popular strategies are local and batched evaluat...
159
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IPPS
2009
IEEE
16 years 1 months ago
2009
IEEE
In the past few years, there has been a trend of providing increased computing power through greater number of cores on a chip, rather than through higher clock speeds. In order t...