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229
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PPL
2008
15 years 6 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
219
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ICDCS
2009
IEEE
15 years 4 months ago
2009
IEEE
The email volume per mailbox has largely remained low and unchanged in the past several decades, and hence mail server performance has largely remained a secondary issue. The stee...
243
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ISCA
2011
IEEE
14 years 10 months ago
2011
IEEE
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
209
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PDP
2011
IEEE
14 years 10 months ago
2011
IEEE
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
182
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...