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FPL
2005
Springer
140views Hardware» more  FPL 2005»
16 years 10 days ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
ICWL
2005
Springer
16 years 10 days ago
Building Learning Management Systems Using IMS Standards: Architecture of a Manifest Driven Approach
Among the existing web-based Learning Management Systems (LMSs), there is an exponentially increasing need of content interoperability. This has caused the apparition of different ...
José Luis Sierra, Pablo Moreno-Ger, Iv&aacu...
IWANN
2005
Springer
16 years 9 days ago
Co-evolutionary Learning in Liquid Architectures
A large class of problems requires real-time processing of complex temporal inputs in real-time. These are difficult tasks for state-of-the-art techniques, since they require captu...
Igal Raichelgauz, Karina Odinaev, Yehoshua Y. Zeev...
ASPLOS
2004
ACM
16 years 7 days ago
Scalable selective re-execution for EDGE architectures
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
Rajagopalan Desikan, Simha Sethumadhavan, Doug Bur...
FPGA
2004
ACM
147views FPGA» more  FPGA 2004»
16 years 6 days ago
The SFRA: a corner-turn FPGA architecture
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
Nicholas Weaver, John R. Hauser, John Wawrzynek