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ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
16 years 1 months ago
A low-area interconnect architecture for chip multiprocessors
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
Zhiyi Yu, Bevan M. Baas
ICCCN
2007
IEEE
16 years 1 months ago
Design of a Network Service Architecture
— Considerable research efforts in the networking community are focused on defining a new Internet architecture that not only solves some of the problems of the current design, ...
Sivakumar Ganapathy, Tilman Wolf
SIPS
2007
IEEE
16 years 29 days ago
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
ADAEUROPE
2007
Springer
16 years 27 days ago
Sancta: An Ada 2005 General-Purpose Architecture for Mobile Robotics Research
Abstract. We present Sancta, a flexible control architecture for multirobot teams. It is fully written in Ada 2005, except for the reuse of some C libraries. In this paper we high...
Alejandro R. Mosteo, Luis Montano
ASAP
2006
IEEE
145views Hardware» more  ASAP 2006»
16 years 23 days ago
2D-VLIW: An Architecture Based on the Geometry of Computation
This work proposes a new architecture and execution model called 2D-VLIW. This architecture adopts an execution model based on large pieces of computation running over a matrix of...
Ricardo Santos, Rodolfo Azevedo, Guido Araujo