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ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
15 years 10 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
ARVLSI
1995
IEEE
146views VLSI» more  ARVLSI 1995»
15 years 10 months ago
Array-of-arrays architecture for parallel floating point multiplication
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
H. Dhanesha, K. Falakshahi, Mark Horowitz
AINA
2005
IEEE
15 years 8 months ago
Traffic Aggregation Based SIP over MPLS Network Architecture
—In this paper, a traffic aggregation based SIP over MPLS network architecture is proposed to integrate SIP protocol with traffic engineering (TE) enabled MPLS network seamlessly...
Bo Rong, Jacques Lebeau, Maria Bennani, Michel Kad...
ACL
2003
15 years 8 months ago
Integrating Discourse Markers into a Pipelined Natural Language Generation Architecture
Pipelined Natural Language Generation (NLG) systems have grown increasingly complex as architectural modules were added to support language functionalities such as referring expre...
Charles B. Callaway
ISICT
2004
15 years 8 months ago
The design of the IPACS distributed software architecture
The IPACS-project (Integrated Performance Analysis of Computer Systems) was founded by the Federal Department of Education, Science, Research and Technology (BMBF) in the program ...
Heinz Kredel, Matthias Merz