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JPDC
2006
141views more  JPDC 2006»
15 years 6 months ago
M-TREE: A high efficiency security architecture for protecting integrity and privacy of software
Secure processor architectures enable new sets of applications such as commercial grid computing, software copy protection and secure mobile agents by providing secure computing e...
Chenghuai Lu, Tao Zhang, Weidong Shi, Hsien-Hsin S...
ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
16 years 3 months ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
3DIC
2009
IEEE
184views Hardware» more  3DIC 2009»
16 years 1 months ago
Architectural evaluation of 3D stacked RRAM caches
The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resis...
Dean L. Lewis, HsienHsin S. Lee
LCN
2008
IEEE
16 years 1 months ago
IPclip: An architecture to restore Trust-by-Wire in packet-switched networks
—During the last decades, the Internet has steadily developed into a mass medium. The target group radically changed compared to, e.g., the 90s. Because virtually everyone has ac...
Harald Widiger, Stephan Kubisch, Peter Danielis, J...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
16 years 1 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...