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153
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USENIX
2007
15 years 9 months ago
2007
This paper presents SafeStore, a distributed storage system designed to maintain long-term data durability despite conventional hardware and software faults, environmental disrupt...
200
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ISCA
2010
IEEE
15 years 8 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
181
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CF
2005
ACM
15 years 8 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
214
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CNSR
2005
IEEE
15 years 8 months ago
2005
IEEE
The dramatic increase in the number of mobile subscribers has put a significant resource and service provisioning strain on current cellular networks in particular in terms of mu...
221
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CASES
2007
ACM
15 years 8 months ago
2007
ACM
Aggressive compiler optimizations such as software pipelining and loop invariant code motion can significantly improve application performance, but these transformations often re...