The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
At the Leiden Embedded Research Center, we are developing a compiler called Compaan that automatically translates signal processing applications written in Matlab into Kahn Proces...
The use of AC coupled interconnects to provide communication paths between devices is increasing. The existing IEEE 1149.1 boundary scan standard [1] (JTAG) has limitations that h...
This paper reports on the use of coordination contracts, presented at the previous two IWPSE workshops, in a project for a credit recovery company. We have designed and implemente...
Michel Wermelinger, Georgios Koutsoukos, Richard A...