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IPPS
2007
IEEE
16 years 1 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
DATE
2006
IEEE
202views Hardware» more  DATE 2006»
16 years 25 days ago
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
Nico Bannow, Karsten Haug, Wolfgang Rosenstiel
164
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GLOBECOM
2006
IEEE
16 years 25 days ago
Interleaved Multistage Switching Fabrics for Scalable High Performance Routers
As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay late...
Rongsen He, José G. Delgado-Frias
IEEEPACT
2006
IEEE
16 years 24 days ago
Complexity-based program phase analysis and classification
Modeling and analysis of program behavior are at the foundation of computer system design and optimization. As computer systems become more adaptive, their efficiency increasingly...
Chang-Burm Cho, Tao Li
IEEEPACT
2006
IEEE
16 years 24 days ago
Two-level mapping based cache index selection for packet forwarding engines
Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the ...
Kaushik Rajan, Ramaswamy Govindarajan
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